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CPCNG Notes: IDE interface PDF Print E-mail
Written by Hans Summers   
Monday, 25 January 2010 20:04

This page describes the proposed IDE hard disk interface. The IDE specification is simpler than SCSI so has been chosen for the prototype. The IDE interface would be almost trivial but for the fact that the IDE databus is 16 bits wide, whereas the eZ80 data bus is only 8 bits wide. It is possible to connect only 8 bits of the IDE bus directly to the eZ80 data bus, but doing this sacrifices half the capacity of the disk drive.

The solution here is to buffer the high byte of the data word in an 8-bit latch, which is read/written to on an additional port number. There are a number of examples of this on the internet, with circuit diagrams and sample code (see list of links below). The information and circuit described here are derived from these project pages. Below is the draft circuit diagram.

The IDE registers are mapped to eZ80 I/O addresses in the range &0020 to &002F. The high byte is written or read on port &0028. When writing a byte, the high byte register must be written prior to writing the low byte (&0020) so that it is available for sending to the disk drive, which occurs on writing to &0020. Similarly, reading from port &0020 reads the low byte and latches the high byte from the disk drive, which can then be read from port &0028.

CPC NG I/O Addresses for IDE Registers

The following table describes the port mapping of the IDE interface:

Port Register Function
&0020 IDELO Data Port (low byte)
&0021 IDEERR Read: Error Register; Write: Precomp
&0022 IDESECTC Sector Count
&0023 IDESECTN Sector Number
&0024 IDECYLLO Cylinder Low
&0025 IDECYLHI Cylinder High
&0026 IDEHEAD Drive/Head
&0027 IDESTTS Read: Status; Write: Command
&0028 IDEHI Data Port (High Byte)
Not Used
Not Used
Not Used
Not Used
Not Used
&002E IDECTRL Read: Alternative Status; Write; Device Control
&002F IDEADDR Drive Address (Read Only)

IDE Project Links

These are links to IDE projects with circuit diagrams, information, sample code and more. All about the GIDE interface ZX81 Harddisc IDE bus interface circuit BBC IDE interface IDE interface for the Commodore 64/128 8051 IDE Hard Drive Interface IDE Harddisk project for the Amiga 500 IDE Devices on 8-bit machines IDE Project Chirs Ward's 6502 Computer system (incl IDE) Spectrum Hardware DIY: IDE interface Spectrum IDE interface (in Czeckoslovakian) 48K ZX Spectrum expansion system 48K ZX Spectrum expansion system (mirror)

IDE Register descriptions

This section describes the IDE register useage.

&0021 (write): Write Precomp: A write to this port sets the "Write Precompensation Cylinder divided by 4". Not sure what this means.

&0021 (read): Error Register: The contents of the error register when in diagnostic mode are shown in this table:

Value Error
1 No Error detected
2 Formatter device error
3 Sector buffer error
4 ECC circuitry error
5 Controlling microprocessor error

The contents of the error register (read &0021) when in operation mode are shown in this table:

Bit Value Meaning
0 0 DAM found

1 DAM not found
1 0 Track 000 found

1 Track 000 not found
2 0 Command completed

1 Command aborted
3 0 Reserved
4 0 ID found

1 ID not found
5 0 Reserved
6 0 No error

1 Uncorrectable ECC error
7 0 Block OK

1 Bad Block detected

&0026: Drive/Head: Bit 4 of the drive/head register selects drive 0 or drive 1, and bits 3-0 select the head.

&0027 (read): Status: Bits in the status register are set to 1 to indicate one of the following conditions:

Bit Condition
0 Previous command ended in an error
1 Index: set to 1 each disk revolution
2 Disk data read successfully corrected
3 Sector buffer requires servicing
4 Seek complete
5 Write fault
6 Drive is ready
7 Controller is executing a command

&0027 (write): Command: Writes to the command register are as follows:

Command Function
98 E5 check power mode (IDE)
90 execute drive diagnostics
50 format track
EC identify drive (IDE)
97 E3 idle (IDE)
95 E1 idle immediate (IDE)
91 initialise drive parameters
1x recalibrate
E4 read buffer (IDE)
C8 read DMA with retry (IDE)
C9 read DMA without retry (IDE)
C4 read multiples (IDE)
20 read sectors with retry
21 read sectors without retry
22 read long with retry
23 read long without retry
40 read verify sectors with retry
41 read verify sectors without retry
7x seek
EF set features (IDE)
C6 set multiple mode (IDE)
99 E6 set sleep mode (IDE)
96 E2 standby (IDE)
94 E0 standby immediate (IDE)
E8 write buffer (IDE)
CA write DMA with retry (IDE)
CB write DMA with retry (IDE)
C5 write multiple (IDE)
E9 write same (IDE)
30 write sectors with retry
31 write sectors without retry
32 write long with retry
33 write long without retry
3C write verify (IDE)
9A vendor unique (IDE)
C0-C3 vendor unique (IDE)
8x vendor unique (IDE)
F0-F4 EATA standard (IDE)
F5-FF vendor unique (IDE)
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